1. Field of the Invention
The present invention relates to a circuit substrate and a circuit substrate manufacturing method and, in particular, to a circuit substrate on which an electronic component is to be mounted and a circuit substrate manufacturing method.
2. Description of the Related Art
Conventionally, when mounting an electronic component, such as an IC, on a circuit substrate, a mounting method as described below has been performed. Flat electrode pads are formed in an array on the main surface of the circuit substrate. On the other hand, solder bumps are formed in an array on the main surface of the IC. The IC is placed on the circuit substrate in such a manner that the solder bumps are positioned on the electrode pads, and then reflow is performed. Thus, the solder bumps are molten and then the solder bumps and electrode pads are fixed to each other. In this way, the IC is mounted on the circuit substrate.
However, when performing the above-mentioned mounting method, for example, the circuit substrate may become distorted by heat, since the thermal expansion coefficient of the circuit substrate is different from that of the IC. Thus, the circuit substrate and IC may make a poor connection with each other. For this reason, for semiconductor element substrates described in Patent Japanese Patent Publication No. 3203731 and Japanese Unexamined Patent Application Publication No. 08-88470, instead of flat electrode pads, column-shaped bumps are formed on the semiconductor element substrate so as to protrude from the main surface of the semiconductor element substrate.
Since the column-shaped bumps have a height unlike electrode pads, they have expansion/contraction properties.
Therefore, even if the circuit substrate becomes distorted by heat, the column-shaped bumps can absorb the distortion. As a result, the semiconductor element substrates described in Japanese Patent Publication No. 3203731 and Japanese Unexamined Patent Application Publication No. 08-88470 can prevent a poor connection between the circuit substrate and IC.
However, the above-mentioned semiconductor element substrates have a problem in that it is difficult to mount the IC on the circuit substrate accurately. Explanation will be made below with reference to the drawings. FIGS. 11A and 11B illustrate a portion of the process of mounting an IC 104 on a semiconductor element substrate 100.
As for the semiconductor element substrate 100, the IC 104 must be placed on the semiconductor element substrate 100 in such a manner that solder bumps 106 are aligned with column-shaped bumps 102, and then reflow must be performed.
However, due to formation accuracy of the column-shaped bumps 102 and solder bumps 106, distortion of the semiconductor element substrate 100, variations in the placement accuracy of the IC 104, or the like, the solder bumps 106 may be placed on the column-shaped bumps 102 so as to be misaligned with respect to the column-shaped bumps as shown in FIG. 11A. If the solder bumps 106 are placed on the column-shaped bumps 102 in a misaligned manner with respect to the column-shaped bumps as described above, the column-shaped bumps 102 and solder bumps 106 may lose contact with each other as shown in FIG. 11B due to shock applied during the period from the placement to reflow. When performing reflow in this state, the semiconductor element substrate 100 and IC 104 will make a poor connection with each other.